Circuit/System Description

The chassis high speed GMLAN bus functions the same as the primary high speed GMLAN bus, and the two buses operate in parallel. The chassis high speed GMLAN bus is added to reduce message congestion on the primary high speed bus. Since the chassis high speed GMLAN bus and primary high speed GMLAN bus operate in the same manner, the diagnostics for each are the same.

The serial data is transmitted on two twisted wires that allow speeds up to 500 kbit/s. The twisted pair is terminated with two 120 Ω resistors, one is internal to the electronic brake control module and the other can be a separate resistor in a connector assembly or in another device. The resistors are used as the load for the chassis high speed GMLAN bus during normal vehicle operation. The chassis high speed GMLAN is a differential bus. The chassis high speed GMLAN serial data bus (+) and chassis high speed GMLAN serial data (-) are driven to opposite extremes from a rest or idle level of approximately 2.5 V. Driving the lines to their extremes, adds 1 V to the chassis high speed GMLAN serial data bus (+) circuit and subtracts 1 V from the chassis high speed GMLAN serial data bus (-) circuit. If serial data is lost, devices will set a no communication code against the non-communicating device. Note that a loss of serial data DTC does not represent a failure of the device that set it.